Verilog preprocessor: implement multi-line defines #77
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This implements multi-line macros in the Verilog preprocessor.
| @@ -362,13 +362,23 @@ void verilog_preprocessort::directive() | |||
| // skip whitespace | |||
| tokenizer().skip_ws(); | |||
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| // Read any tokens until end of line. | |||
| // Read any tokens until end of line, | |||
| // but note that \n can be escaped with a backslash. | |||
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Shouldn't verilog_preprocessor_token_sourcet::skip_until_eol also learn about this?
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Unfortunately the standard is very unclear under which circumstances this is supposed to happen. I'll need to experiment with some standard tools.
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If this is global, it might be preferable to move the escaping into the flex tokenizer.
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Yes, it might need to move into the tokenizer.
https://www.cs.utexas.edu/users/moore/acl2/manuals/current/manual/index-seo.php/VL____LEX-STRINGS
| auto nl = tokenizer().next_token(); | ||
| define.tokens.push_back(std::move(nl)); | ||
| } | ||
| else | ||
| define.tokens.push_back(std::move(token)); |
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Probably a matter of taste:
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token = tokenizer().next_token();
}
define.tokens.push_back(std::move(token));
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Indeed a matter of taste; I do feel that the longer version is quicker to understand.
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Also, are we still getting line numbers right in any warnings/errors affecting lines after a multi-line define? |
Yes, the line counting happens in the tokenizer. |
Right instinct; while the line counting in the preprocessor works, the line counting in the parser is off. |
This implements multi-line macros in the Verilog preprocessor.